There is a strict requirement for phase error with respect to efficient digital modulated signals applied in a high speed communication system, which requires that the phase error between a transmitter and a receiver is controlled in a small range during the reception and modulation to ensure the sensitivity of demodulation.
Specifically, a TETRA (Trans European Trunked Radio) protocol is a standard protocol used widely in trunked channels, for which the modulation mode DQPSK (Differential Quadrature Reference Phase Shift Keying) is used. In order to ensure the sensitivity of reception in the system, the timing difference in the synchronization of symbols is defined in a range of −0.25 symbol to +0.25 symbol in the TETRA protocol.
The main functions of the receiver include carrier synchronization and clock synchronization. In order to control the timing difference in the synchronization of symbols in the range defined in the TETRA protocol, a local sampling clock used for modulation in the all-digital receiver oscillates at a fixed frequency, the calculation of carrier phase error and bit clock error, the estimation of an optimal decision point and the decision of symbols are all achieved by a sampled digital signal processer, and then adjustment is performed by NCO (Numerical Controlled Oscillator) in the conventional technology. Therefore, the difficulty in an early feedback control to analog component by a receiver and in the design of phase locked loop for efficient transmission can be avoided.
The inventors have studied and found that there are at least the following disadvantages for the all-digital receiver in the conventional technology.
In order to ensure the synchronization of all local clocks, generally all clocks of the all-digital receiver in the conventional technology are required to be led out from the same clock source. In most cases, different clock frequencies are required for a baseband processing chip and a DSP (digital signal processing) respectively. An expensive dedicated crystal oscillator is required for leading out the baseband processing chip and the DSP, which respectively require different clock frequencies, from the same clock source, therefore the cost of the all-digital receiver is increased.